CDCLVP1212RHAR

Texas Instruments Incorporated

CDCLVP1212RHAR

Availability

Design risk

Price trend

Lead time

Semiconductors

Timers or RTCs

Lead time 6 weeks
Data sheet CDCLVP1212RHAR
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Availability

Design risk

Price trend

Lead time

Semiconductors

Timers or RTCs

Lead time 6 weeks
Data sheet CDCLVP1212RHAR

Low jitter, 2-input selectable 1:12 universal-to-LVPECL buffer 40-VQFN -40 to 85

Technical Data
Family CDC
Width (mm) 6
Length (mm) 6
JESD-30 Code S-PQCC-N40
Package Code HVQCCN
Logic IC Type LOW SKEW CLOCK DRIVER
Package Shape SQUARE
Package Style (Meter) CHIP CARRIER
Surface Mount YES
Terminal Form NO LEAD
J-STD-609 Code e4
Packing Method TR
fmax-Min (MHz) 2000.0000
Terminal Finish Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)
DLA Qualification Not Qualified
Temperature Grade INDUSTRIAL
Terminal Position QUAD
Input Conditioning DIFFERENTIAL MUX
Number of Functions 1
Number of Terminals 40
Terminal Pitch (mm) 0.5
Package Body Material PLASTIC/EPOXY
Number of True Outputs 12
Output Characteristics OPEN-EMITTER
Propagation Delay (ns) 0.5500
Seated Height-Max (mm) 1
Supply Voltage-Max (V) 3.6
Supply Voltage-Min (V) 2.375
Supply Voltage-Nom (V) 2.5
Supply Current-Max (mA) 88
Package Equivalence Code LCC40,.24SQ,20
Moisture Sensitivity Level 3
Number of Inverted Outputs 0
Peak Reflow Temperature (Cel) 260
Operating Temperature-Max (Cel) 85
Operating Temperature-Min (Cel) -40
Propagation Delay-Max@Nom-Sup (ns) 0.550000000000000000
Same Edge Clock Skew Delay-Max (ns) 0.0250
Time@Peak Reflow Temperature-Max (s) 30

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