LTC3204BEDC-5#TRMPBF

Analog Devices, Inc.

LTC3204BEDC-5#TRMPBF

Availability

Design risk

Price trend

Lead time

Semiconductors

Power Management Circuits

Lead time 6 weeks
11 results found

Availability

Design risk

Price trend

Lead time

Semiconductors

Power Management Circuits

Lead time 6 weeks

Low Noise Regulated Charge Pump in 2 × 2 DFN

Technical Data
Technology CMOS
Width (mm) 2
Length (mm) 2
JESD-30 Code S-PDSO-N6
Package Code HVSON
Package Shape SQUARE
Package Style (Meter) SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
Surface Mount YES
Terminal Form NO LEAD
J-STD-609 Code e3
Terminal Finish Matte Tin (Sn)
DLA Qualification Not Qualified
Temperature Grade COMMERCIAL
Terminal Position DUAL
Number of Functions 1
Number of Terminals 6
Terminal Pitch (mm) 0.5
Input Voltage-Max (V) 5.5
Input Voltage-Min (V) 2.7
Input Voltage-Nom (V) 3.6
Package Body Material PLASTIC/EPOXY
Analog IC - Other Type SWITCHED CAPACITOR REGULATOR
Output Current-Max (A) 0.3
Seated Height-Max (mm) 0.8
Switcher Configuration DOUBLER INVERTER
Moisture Sensitivity Level 1
Peak Reflow Temperature (Cel) 260
Switching Frequency-Max (kHz) 1800
Operating Temperature-Max (Cel) 70
Operating Temperature-Min (Cel) 0
Time@Peak Reflow Temperature-Max (s) 30

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Sourceability North America, LLC

9715 Burnet Rd, Ste 200
Austin, TX 78758-5215