XC3S500E-4FTG256C
Availability
Design risk
Price trend
Lead time
FPGA Spartan-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 256-Pin FTBGA
Technology | CMOS |
Width (mm) | 17 |
Length (mm) | 17 |
JESD-30 Code | S-PBGA-B256 |
Organization | 1164 CLBS, 500000 GATES |
Package Code | LBGA |
Package Shape | SQUARE |
Package Style (Meter) | GRID ARRAY, LOW PROFILE |
Surface Mount | YES |
Terminal Form | BALL |
J-STD-609 Code | e1 |
Number of CLBs | 1164 |
Terminal Finish | TIN SILVER COPPER |
Number of Inputs | 190 |
DLA Qualification | Not Qualified |
Number of Outputs | 149 |
Temperature Grade | OTHER |
Terminal Position | BOTTOM |
Number of Terminals | 256 |
Terminal Pitch (mm) | 1 |
Number of Logic Cells | 10476 |
Package Body Material | PLASTIC/EPOXY |
Seated Height-Max (mm) | 1.55 |
Supply Voltage-Max (V) | 1.26 |
Supply Voltage-Min (V) | 1.14 |
Supply Voltage-Nom (V) | 1.2 |
Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY |
Package Equivalence Code | BGA256,16X16,40 |
Clock Frequency-Max (MHz) | 572 |
Moisture Sensitivity Level | 3 |
Number of Equivalent Gates | 500000 |
Peak Reflow Temperature (Cel) | 260 |
Operating Temperature-Max (Cel) | 85 |
Operating Temperature-Min (Cel) | 0 |
Time@Peak Reflow Temperature-Max (s) | 30 |
Combinatorial Delay of a CLB-Max (ns) | 0.76 |
Submit request
CONTACT REASON
Sourceability North America, LLC
9715 Burnet Rd, Ste 200