OPA2140AIDGKR

Texas Instruments Incorporated

OPA2140AIDGKR

Availability

Design risk

Price trend

Lead time

Semiconductors

Buffer Amplifiers

Lead time 6 weeks
Data sheet OPA2140AIDGKR
1 results found

Availability

Design risk

Price trend

Lead time

Semiconductors

Buffer Amplifiers

Lead time 6 weeks
Data sheet OPA2140AIDGKR

Dual-channel, 11-MHz, low-noise 36-V JFET precision operational amplifier with rail-to-rail output 8-VSSOP -40 to 125

Technical Data
Power NO
Low-Bias YES
Wideband NO
Low-Offset YES
Micropower NO
Technology JFET
Width (mm) 3
Length (mm) 3
JESD-30 Code S-PDSO-G8
Package Code TSSOP
Package Shape SQUARE
Package Style (Meter) SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Surface Mount YES
Terminal Form GULL WING
Amplifier Type J-FET
J-STD-609 Code e4
Packing Method TR, 13 INCH
Terminal Finish Nickel/Palladium/Gold (Ni/Pd/Au)
Amp Architecture VOLTAGE-FEEDBACK
Voltage Gain-Min 501187.2336
DLA Qualification Not Qualified
Temperature Grade AUTOMOTIVE
Terminal Position DUAL
Programmable Power NO
Number of Functions 2
Number of Terminals 8
Terminal Pitch (mm) 0.65
Slew Rate-Nom (V/us) 20
Package Body Material PLASTIC/EPOXY
Frequency Compensation YES
Seated Height-Max (mm) 1.1
Supply Current-Max (mA) 5.4
Unity Gain BW-Nom (kHz) 11000
Package Equivalence Code TSSOP8,.19
Moisture Sensitivity Level 2
Supply Voltage Limit-Max (V) 20
Input Offset Voltage-Max (uV) 120
Peak Reflow Temperature (Cel) 260
Operating Temperature-Max (Cel) 125
Operating Temperature-Min (Cel) -40
Bias Current-Max (IIB) @25C (uA) 1.0E-5
Neg Supply Voltage Limit-Max (V) -20
Common-mode Reject Ratio-Min (dB) 126
Common-mode Reject Ratio-Nom (dB) 140
Average Bias Current-Max (IIB) (uA) 0.003
Input Offset Current-Max (IIO) (uA) 0.001
Time@Peak Reflow Temperature-Max (s) 30

Submit request

CONTACT REASON

Connect with us

Sourceability North America, LLC

9715 Burnet Rd, Ste 200
Austin, TX 78758-5215