NL17SZ00DFT2G

ONSEMI

NL17SZ00DFT2G

Availability

Design risk

Price trend

Lead time

Semiconductors

Gates

Lead time 6 weeks
Data sheet NL17SZ00DFT2G
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Availability

Design risk

Price trend

Lead time

Semiconductors

Gates

Lead time 6 weeks
Data sheet NL17SZ00DFT2G

NAND Gate 1-Element 2-IN CMOS 5-Pin SC-88A T/R

Technical Data
Family LVC/LCX/Z
Technology CMOS
Width (mm) 1.25
Length (mm) 2
JESD-30 Code R-PDSO-G5
Package Code TSSOP
Logic IC Type NAND GATE
Package Shape RECTANGULAR
Package Style (Meter) SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Surface Mount YES
Terminal Form GULL WING
J-STD-609 Code e3
Packing Method TR
Schmitt Trigger NO
Terminal Finish Matte Tin (Sn) - annealed
Number of Inputs 2
DLA Qualification Not Qualified
Temperature Grade MILITARY
Terminal Position DUAL
Number of Functions 1
Number of Terminals 5
Terminal Pitch (mm) 0.65
Load Capacitance (pF) 50
Package Body Material PLASTIC/EPOXY
Propagation Delay (ns) 12
Seated Height-Max (mm) 1.1
Supply Voltage-Max (V) 5.5
Supply Voltage-Min (V) 1.65
Supply Voltage-Nom (V) 1.8
Supply Current-Max (mA) 0.01
Package Equivalence Code TSSOP5/6,.08
Moisture Sensitivity Level 1
Output Low Current-Max (mA) 24
Peak Reflow Temperature (Cel) 260
Operating Temperature-Max (Cel) 125
Operating Temperature-Min (Cel) -55
Propagation Delay-Max@Nom-Sup (ns) 5.2
Time@Peak Reflow Temperature-Max (s) 40

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