PDTC114YT,215

Nexperia BV

PDTC114YT,215

Availability

Design risk

Price trend

Lead time

Semiconductors

Power Bipolar Transistors

Lead time 6 weeks
Data sheet PDTC114YT,215
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Availability

Design risk

Price trend

Lead time

Semiconductors

Power Bipolar Transistors

Lead time 6 weeks
Data sheet PDTC114YT,215

50 V, 100 mA NPN resistor-equipped transistor; R1 = 10 kΩ, R2 = 47 kΩ

Technical Data
Application SWITCHING
JESD-30 Code R-PDSO-G3
Configuration SINGLE WITH BUILT-IN RESISTOR
JEDEC-95 Code TO-236AB
Package Shape RECTANGULAR
Package Style SOT-23 (SC-59,TO-236)
Surface Mount YES
Terminal Form GULL WING
J-STD-609 Code e3
VCEsat-Max (V) 0.3
Terminal Finish TIN
DLA Qualification Not Qualified
Terminal Position DUAL
Additional Feature BUILT IN BIAS RESISTANCE RATIO IS 4.7
Number of Elements 1
Number of Terminals 3
Package Body Material PLASTIC/EPOXY
Polarity/Channel Type NPN
DC Current Gain-Min (hFE) 100
Moisture Sensitivity Level 1
Transistor Element Material SILICON
Peak Reflow Temperature (Cel) 260
Collector Current-Max (IC) (A) 0.1
Operating Temperature-Max (Cel) 150
Collector-emitter Voltage-Max (V) 50
Power Dissipation Ambient-Max (W) 0.25
Collector-base Capacitance-Max (pF) 3.5
Screening Level / Reference Standard IEC-60134
Time@Peak Reflow Temperature-Max (s) 30

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