CY7C68013A-128AXC

CYPRESS SEMICONDUCTOR CORP

CY7C68013A-128AXC
 
CY7C68013A-128AXC

CY7C68013A-128AXC

Availability
Unavailable
Availability
Design risk
Medium
Design risk
Price trend
Decreasing
Price trend
Lead time
Stable
Lead time
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Semiconductors

Bus Controllers

Lead Time     2 weeks
Data Sheet     Download CY7C68013A-128AXC datasheet CY7C68013A-128AXC

Interfaces ICs, CY7C68013A-128AXC, Cypress The CY7C68013A is identical to CY7C68014A in form, fit, and functionality. Two additional GPIO signals are available to provide more flexibility when neither IFCLK or CLKOUT are needed, the two GPIOs give developers the signals they need for the power-control circuitry of their bus-powered application without pushing them to a high-pincount version of FX2LP. Features USB 2.0 USB IF Hi-Speed certified Ultra-low power: ICC no more than 85 mA in any mode Four programmable BULK, INTERRUPT, and ISOCHRONOUS endpoints Smart media standard ECC generation 8-bit or 16-bit external data interface

Technical Data

Manufacturer cypress semiconductor corp
MPN CY7C68013A-128AXC
Bit Size 8.0000
CPU Family 8051.0000
Technology CMOS
Width (mm) 14.0000
Length (mm) 20.0000
Speed (MHz) 48.0000
ADC Channels NO
DAC Channels NO
DMA Channels NO
JESD-30 Code R-PQFP-G128
PWM Channels NO
Package Code LFQFP
Package Shape RECTANGULAR
Package Style ( Meter ) FLATPACK, LOW PROFILE, FINE PITCH
Surface Mount YES
Terminal Form GULL WING
J-STD-609 Code e3
Terminal Finish Matte Tin (Sn)
Address Bus Width 16.0000
Bus Compatibility I2C; UART; USB
DLA Qualification Not Qualified
Temperature Grade COMMERCIAL
Terminal Position QUAD
Number of I/O Lines 40.0000
Number of Terminals 128.0000
Program Memory Type EEPROM
Terminal Pitch (mm) 0.5000
Data RAM Size (bytes) 16384.0000
Package Body Material PLASTIC/EPOXY
Seated Height-Max (mm) 1.6000
Supply Voltage-Max (V) 3.6000
Supply Voltage-Min (V) 3.0000
Supply Voltage-Nom (V) 3.3000
External Data Bus Width 8.0000
Supply Current-Max (mA) 85.0000
Package Equivalence Code QFP128,.63X.87,20
Clock Frequency-Max (MHz) 24.0000
Moisture Sensitivity Level 3.0000
uPs/uCs/Peripheral ICs Type BUS CONTROLLER, UNIVERSAL SERIAL BUS
Data Transfer Rate-Max (MBps) 60.0000
Peak Reflow Temperature (Cel) 260.0000
Operating Temperature-Max (Cel) 70.0000
Operating Temperature-Min (Cel) 0.0000
Time@Peak Reflow Temperature-Max (s) 20.0000
Availability In stock

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9715 Burnet Rd, Ste 200 Austin, TX 78758-5215

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Phone +1-888-952-9225

Frequently Asked Questions

As part of the category Semiconductors and subcategory Bus Controllers, CY7C68013A-128AXC optimizes energy distribution in electronic devices. Its Interfaces ICs, CY7C68013A-128AXC, Cypress The CY7C68013A is identical to CY7C68014A in form, fit, and functionality. Two additional GPIO signals are available to provide more flexibility when neither IFCLK or CLKOUT are needed, the two GPIOs give developers the signals they need for the power-control circuitry of their bus-powered application without pushing them to a high-pincount version of FX2LP. Features USB 2.0 USB IF Hi-Speed certified Ultra-low power: ICC no more than 85 mA in any mode Four programmable BULK, INTERRUPT, and ISOCHRONOUS endpoints Smart media standard ECC generation 8-bit or 16-bit external data interface allows minimizing losses and increasing the overall system efficiency.

As a component of the subcategory Bus Controllers, CY7C68013A-128AXC ensures stable output voltage even when the load changes. Its makes it a reliable element in multi-level power systems.

You can download the user manual and technical specifications for CY7C68013A-128AXC in the documentation section.

Interfaces ICs, CY7C68013A-128AXC, Cypress The CY7C68013A is identical to CY7C68014A in form, fit, and functionality. Two additional GPIO signals are available to provide more flexibility when neither IFCLK or CLKOUT are needed, the two GPIOs give developers the signals they need for the power-control circuitry of their bus-powered application without pushing them to a high-pincount version of FX2LP. Features USB 2.0 USB IF Hi-Speed certified Ultra-low power: ICC no more than 85 mA in any mode Four programmable BULK, INTERRUPT, and ISOCHRONOUS endpoints Smart media standard ECC generation 8-bit or 16-bit external data interface

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