EP2C8Q208I8N
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FPGA - Field Programmable Gate Array
| Technology | CMOS |
| Width (mm) | 28 |
| Length (mm) | 28 |
| JESD-30 Code | S-PQFP-G208 |
| Organization | 516 CLBS |
| Package Code | FQFP |
| Package Shape | SQUARE |
| Package Style (Meter) | FLATPACK, FINE PITCH |
| Surface Mount | YES |
| Terminal Form | GULL WING |
| J-STD-609 Code | e3 |
| Number of CLBs | 516 |
| Terminal Finish | MATTE TIN |
| Number of Inputs | 138 |
| DLA Qualification | Not Qualified |
| Number of Outputs | 130 |
| Terminal Position | QUAD |
| Additional Feature | ALSO REQUIRES 3.3 SUPPLY |
| Number of Terminals | 208 |
| Terminal Pitch (mm) | 0.5 |
| Number of Logic Cells | 8256 |
| Package Body Material | PLASTIC/EPOXY |
| Seated Height-Max (mm) | 4.1 |
| Supply Voltage-Max (V) | 1.25 |
| Supply Voltage-Min (V) | 1.15 |
| Supply Voltage-Nom (V) | 1.2 |
| Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY |
| Package Equivalence Code | QFP208,1.2SQ,20 |
| Clock Frequency-Max (MHz) | 402.5 |
| Moisture Sensitivity Level | 3 |
| Peak Reflow Temperature (Cel) | 245 |
| Time@Peak Reflow Temperature-Max (s) | 30 |
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CONTACT REASON
Sourceability North America, LLC
9715 Burnet Rd, Ste 200You can download the user manual and technical specifications for ALTERA CORP EP2C8Q208I8N in the documentation section.
FPGA - Field Programmable Gate Array
As part of the category Semiconductors and subcategory Semiconductors, EP2C8Q208I8N optimizes energy distribution in electronic devices. Its FPGA - Field Programmable Gate Array allows minimizing losses and increasing the overall system efficiency.
As a component of the subcategory Semiconductors, EP2C8Q208I8N ensures stable output voltage even when the load changes. Its FPGA - Field Programmable Gate Array makes it a reliable element in multi-level power systems.
