XC6SLX100-2FGG484I
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FPGA - Field Programmable Gate Array XC6SLX100-2FGG484I
| Technology | CMOS |
| Width (mm) | 23 |
| Length (mm) | 23 |
| JESD-30 Code | S-PBGA-B484 |
| Organization | 7911 CLBS |
| Package Code | BGA |
| Package Shape | SQUARE |
| Package Style (Meter) | GRID ARRAY |
| Surface Mount | YES |
| Terminal Form | BALL |
| J-STD-609 Code | e1 |
| Number of CLBs | 7911 |
| Terminal Finish | TIN SILVER COPPER |
| Number of Inputs | 326 |
| DLA Qualification | Not Qualified |
| Number of Outputs | 326 |
| Temperature Grade | INDUSTRIAL |
| Terminal Position | BOTTOM |
| Number of Terminals | 484 |
| Terminal Pitch (mm) | 1 |
| Number of Logic Cells | 101261 |
| Package Body Material | PLASTIC/EPOXY |
| Seated Height-Max (mm) | 2.6 |
| Supply Voltage-Max (V) | 1.26 |
| Supply Voltage-Min (V) | 1.14 |
| Supply Voltage-Nom (V) | 1.2 |
| Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY |
| Package Equivalence Code | BGA484,22X22,40 |
| Clock Frequency-Max (MHz) | 667 |
| Moisture Sensitivity Level | 3 |
| Peak Reflow Temperature (Cel) | 250 |
| Operating Temperature-Max (Cel) | 100 |
| Operating Temperature-Min (Cel) | -40 |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Combinatorial Delay of a CLB-Max (ns) | 0.26 |
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CONTACT REASON
Sourceability North America, LLC
9715 Burnet Rd, Ste 200You can download the user manual and technical specifications for Xilinx,Inc. XC6SLX100-2FGG484I in the documentation section.
FPGA - Field Programmable Gate Array XC6SLX100-2FGG484I
As part of the category Semiconductors and subcategory Semiconductors, XC6SLX100-2FGG484I optimizes energy distribution in electronic devices. Its FPGA - Field Programmable Gate Array XC6SLX100-2FGG484I allows minimizing losses and increasing the overall system efficiency.
As a component of the subcategory Semiconductors, XC6SLX100-2FGG484I ensures stable output voltage even when the load changes. Its FPGA - Field Programmable Gate Array XC6SLX100-2FGG484I makes it a reliable element in multi-level power systems.
